The new TSMC packaging promises lower costs and greater efficiency

TSMC (Taiwan Semiconductor Manufacturing Company) is developing an advanced packaging technology named CoPoS, acronym of Chip-on-Panel-on-Structure.

Scheduled to begin mass production in the second half of 2028, this solution promises to significantly reduce manufacturing costs while ensuring a notable increase in processor performance.

The primary application of this novelty will be closely linked to the development of AI chips and high-performance computing, sectors characterized by a continual demand for greater efficiency.

TSMC: CoPoS packaging with three-dimensional architecture and glass

The true peculiarity of the CoPoS process lies in exploiting the properties of glass, which is employed in two distinct and crucial stages of production.

In a first stage, glass sheets measuring 310 x 310 mm act as temporary supports during processing. Subsequently, the material becomes an integral part of the final substrate. The production cycle will pass through pilot formats of 250 x 250 mm, then settle on panels of 510 x 515 mm during large-scale production, from which the individual substrates will be derived.

The final configuration envisions a structure of three stacked layers: the central glass core is enclosed between two ABF (Ajinomoto Build-up Film) accumulation layers. All the complex engineering challenges related to glass processing, such as via formation (TGV) and copper metallization, are concentrated entirely within this multilayer architecture.

There are several inaccuracies circulating around CoPoS technology that require some clarity. The glass used, contrary to what might be assumed, does not play the role of an interposer. The interconnection function is instead delegated to the RDL layer on the processor side, in combination with copper connections and the ABF layers of the substrate.

Moreover, the insertion of glass does not eliminate the need for ABF, but the two components work in close continuity within the architecture. Finally, the chips are not placed in direct contact with the glass surface, but are securely anchored to the ABF surface that coats the central core.

The Nvidia debut and market consolidation

The practical implementation of the CoPoS system is designed to support the physical needs of ultra-large packages, far beyond the 9.5x grid class.

According to tests, Nvidia’s Feynman AI chip is emerging as the first likely candidate for adopting this form factor.

The technical validity of this innovation will allow TSMC to strengthen its global supremacy in the field of advanced packaging, ensuring the company a clear and stable competitive edge estimated at least until 2032, effectively forcing rival companies to rush to propose rapid commercial alternatives.