During the North American Technology Symposium 2026, TSMC (Taiwan Semiconductor Manufacturing Company) outlined its precise roadmap for the second half of the decade.
The strategy revealed by the company rests on an extremely pragmatic approach, which prioritizes advanced optimization of existing resources over adopting new and costly equipment.
In a move widely discussed in the sector, management decided to postpone the use of ASML’s latest High-NA EUV lithography machines, produced by the Dutch ASML, aiming to push the systems currently in use to the limit to achieve extreme miniaturization milestones, such as the future production nodes of 1.3 and 1.2 nm expected for 2029.
TSMC: Optimization of existing ASML machines for 1.2 nm
The choice to delay the introduction of ASML’s new lithography scanners is not linked to doubts about their technical validity, as they are fundamental machines for future generations of semiconductors, but to a rigorous financial assessment.
Currently, the entire microchip industry is directing enormous capital toward building new foundries to address the relentless AI-driven demand. In this context, the prohibitive costs of High-NA EUV machines represent a burden too heavy to bear in the short term.
Kevin Zhang, senior vice president of the Asian company, clarified that the adoption of these new tools will occur exclusively when they guarantee truly measurable advantages. Until then, R&D teams will continue to extend the lifecycles of the current EUV systems, a method that is already delivering substantial improvements in the transistor shrinking phase.
The path to the A13 and A12 nodes
Parallel to the start of mass production of the N2 technology, expected on the first commercial products of this year, the roadmap envisions a path of steady refinements. The 2028 will see the commercial debut of the N2U technology, designed to offer a speed increase of between 2% and 4%, or a near 10% reduction in power consumption, at parity in performance with the N2P variant.
This solution will position itself as a highly balanced option, characterized by very solid production yields, ideal for the high-performance computing and mobile devices sectors.
The following year, 2029, will mark the actual generational leap with the start of production of the most extreme nodes. The A13 1.3 nm process will enable a silicon area saving of 6% compared to its predecessor A14, maintaining with the latter complete backward compatibility and ensuring more compact and efficient architectures.
Almost concurrently, the A12 1.2-nm node will come online, a further level of refinement that will benefit from the Super Power Rail technology for backside power delivery, thereby maximizing the chip’s electrical performance.
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Aware that simply shrinking transistors is no longer enough to deliver the performance leaps demanded by the market, the company is dedicating substantial resources to developing advanced assembly solutions. The proven CoWoS technology, which currently handles components up to 5.5 reticles in size, is subject to a massive expansion plan.
By 2028, production lines will push out CoWoS modules with 14 reticles, capable of integrating 10 computing units and as many as 20 HBM memory blocks. The sizes will grow even more boldly in 2029 with the launch of SoW-X, designed to reach a 40-reticle scale.
These innovations will contend with proprietary solutions being studied by other major players in the field, as illustrated by recent OpenAI patents on the use of integrated interconnection bridges to bypass current 2.5D packaging limits.
The era of photonics and ultra-high-density interconnects
To support the rising data-transfer demands with near-zero latency, the roadmap includes key targets in the field of optical connections.
The TSMC-COUPE project will reach production in 2026, enabling optical engines to be embedded directly within the chip substrate.
This complex integration will deliver double energy efficiency and reduce latency by a factor of 10 compared with traditional external optical connections to the motherboard, relying on a 200 Gigabit-per-second ring modulator designed specifically for data centers.
Furthermore, the three-dimensional stacking architecture SoIC will receive a crucial upgrade in 2029 with direct chip-to-chip connections for A14, designed to offer nearly double the interconnect density compared with the previous generation, thereby ensuring the vast bandwidth required by future chips.
